The present invention relates to an apparatus and method for the peripheral devices of the SRAM; and, more particularly, to an apparatus and method for the refresh and the data input device in the SRAM having storage capacitor cell.
Generally, the dynamic random access memory (DRAM) is widely known as a semiconductor memory device having a memory cell with the capacitor. Since the DRAM includes one access transistor and one capacitor, the DRAM is advantageous in high integration. However, in order to maintain the data stored in the cell, the refresh is required periodically in the DRAM. On the other hand, although the refresh is not required in the static RAM(SRAM) because it operates in a latch type, however, it has disadvantage that the integration is not high as the DRAM because a unit cell has to include the a plurality of transistors.
The pseudo SRAM and the virtual SRAM are widely known for the devices having the advantages of both DRAM and SRAM devices. Although a capacitor is used to store data in a cell, the refresh is concealed easily in both the pseudo SRAM and the virtual SRAM.
On the other hands, when logic xe2x80x98lowxe2x80x99 is applied to a pad/we during the writing operation, the pad/we is transited from xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99 and the data is written in the memory cell after the certain period of time tWC in the SRAM. This is opposite to the DRAM, which writes the data to the cell when the write operation is begun by enabling the pad/we to xe2x80x98lowxe2x80x99.
In the SRAM specification, the limitation for the maximum limit of the writing time is not determined. That means, it is unknown when the writing operation is completed after the pad/we is dropped to xe2x80x98lowxe2x80x99 and the writing operation is begun. Therefore, in case of the SRAM, the refresh is not operated until the data is written into the cell if the refresh in a refresh timer is in turn after the pad/we becomes xe2x80x98lowxe2x80x99. That is because an address from an internal counter is taken by the refresh and the refresh is operated after that, the address from the internal counter is different from the writing address. Furthermore, if the pad/we is transited from xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99 during the refresh, the active address cell is written by the refresh.
Moreover, the fail is occurred if the write operation becomes infinitely longer. Also, the maximum time specification cannot be applied to the write operation because it is not compatible with the ordinary SRAM.
It is, therefore, an object of the present invention to provide an apparatus and method for a refresh and a data input device in SRAM having a storage capacitor cell.
In accordance with an aspect of the present invention, there is provide an apparatus for a refresh and a data input device in the SRAM having a storage capacitor cell, comprising: an internal clock generating means for generating and outputting two internal clock signals having a certain time difference of each other; a refresh timer for generating and outputting an output signal to notify a refresh time; a refresh signal generating means for generating a refresh signal in response to a faster signal of the two internal signals and the output signal from the refresh timer; a refresh counter for generating refresh addresses during the refresh; and a column path control means for controlling the activation of a column path in response to a row active signal and the refresh signal.
In accordance with another aspect of the present invention, there is provide a method for the refresh and the data input device in the SRAM having a storage capacitor cell, comprising the steps of: a) generating two internal clocks having a certain time difference of each other; b) using a delayed signal of the two internal clocks as a strobe signal of an address; c) inputting an output signal from a refresh timer and generating a refresh signal in response to the faster signal of the two internal clocks; and d) selecting one of addresses, which are an external address and an internal address, for using a refresh signal.
In accordance with further another aspect of the present invention, there is provide a method for the refresh and the data input device in the SRAM having a storage capacitor cell, comprising the steps of: a) disabling an address when the refresh signal is enabled during a write operation; b) confirming a current state if it is the write operation when the refresh begins; c) generating a delay signal for notifying the refresh if it is the write operation after the step b); d) generating a write address and a latch signal of the data when the delay signal is generated; e) controlling an external input path of an address buffer using the write latch signal; f) latching an external address after the step e); and g) buffering the latched address after the refresh.
In accordance with further another aspect of the present invention, there is provide a method for the refresh and the data input device in the SRAM having a storage capacitor cell, comprising the steps of: a) disabling an address when the refresh signal is enabled during a write operation; b) confirming the current state if it is the write operation when the refresh begins; c) generating a delay signal for notifying the refresh if it is the write operation after the step b); d) generating a write address and a latch signal of the data when the delay signal is generated; e) controlling a write driver using the write latch signal; f) latching an external address after the step e); and g) buffering the latched address after the refresh.
In accordance with further another aspect of the present invention, there is provide a method for the refresh and the data input device in the SRAM having a storage capacitor cell, comprising the steps of: a) disabling an address when the refresh signal is enabled during a write operation; b) confirming the current state if it is the write operation, when the refresh begins; c) generating a delay signal for notifying the refresh if it is the write operation after the step b); d) generating a write address and a latch signal of the data when the delay signal is generated; e) controlling a write driver using the write latch signal; f) latching an external address after the step e); and g) buffering the latched address after the refresh.
Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.